The present invention relates to electrical timing systems, and more particularly to a delay time checking circuit arrangement.
No means has heretofore been put into practical use or proposed to check whether or not the signal propagation delay time from a point (for instance, a flip-flop (F/F)) in an integrated circuit (IC) chip to another point (for instance, a F/F) in another IC chip is shorter or longer than a predeterminedly allowed time when the IC chips lie on a package substrate or on two respective package substrates.
A logic circuit in a logic circuit package for use in a data processing unit is usually designed to satisfy the condition that the clock cycle of a clock signal t.sub.c fed to the circuit should be greater than an allowed time td.sub.MAX in which a signal must propagate between two F/Fs present in the circuit. Therefore, if the actual signal-propagation (ASP) delay time between the F/Fs in the logic circuit of an actually manufactured data processing unit exceeds the allowed time td.sub.MAX, the unit may operate erroneously. In such a case, this logic circuit is checked. However, for lack of any means to directly detect the ASP delay time between two F/Fs, it takes a long time to locate the operating elements which are causing the trouble.